A hierarchical redundant cube-connected cycle for WSI yield enhancement
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
To enhance system yield for a large scale cube-connected cycle (CCC), we propose a hierarchical redundant architecture in which a cycle is implemented on two rows at the first level and all cycles at the first level are connected as a block in a two dimensional array at the second level. The hierarchical architecture proposed is investigated in area performance and in yield analysis. We show a semantic structure of the CCC and a previous redundant architecture for CCC. A hierarchical CCC architecture to achieve yield enhancement on a silicon wafer is addressed. Performances of the redundant architecture are discussed with respect to layout area and system yield.Keywords
This publication has 10 references indexed in Scilit:
- Yield enhancement designs for WSI cube connected cyclesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Yield enhancement architecture of WSI cube-connected cyclePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A reconfigurable cube-connected cycles architecture for wafer scale integrationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Reconfigurable cube-connected cycles architecturesJournal of Parallel and Distributed Computing, 1990
- The Connection Machine model CM-1 architectureIEEE Transactions on Systems, Man, and Cybernetics, 1989
- Designing interconnection buses in VLSI and WSI for maximum yield and minimum delayIEEE Journal of Solid-State Circuits, 1988
- The cosmic cubeCommunications of the ACM, 1985
- Integrated circuit yield statisticsProceedings of the IEEE, 1983
- The cube-connected cycles: a versatile network for parallel computationCommunications of the ACM, 1981