Yield enhancement designs for WSI cube connected cycles

Publisher Website

7 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/wafer.1989.47559

Abstract

No abstract available

Keywords

This publication has 6 references indexed in Scilit:

Designing interconnection buses in VLSI and WSI for maximum yield and minimum delay
IEEE Journal of Solid-State Circuits, 1988
The cubical ring connected cycles: a fault tolerant parallel computation network
IEEE Transactions on Computers, 1988
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
IEEE Transactions on Computers, 1987
An Array Layout Methodology for VLSI Circuits
IEEE Transactions on Computers, 1986
On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays
IEEE Transactions on Computers, 1984
Integrated circuit yield statistics
Proceedings of the IEEE, 1983