Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
- 1 March 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-36 (3) , 344-355
- https://doi.org/10.1109/tc.1987.1676906
Abstract
The incorporation of different forms of redundancy has been recently proposed for various VLSI and WSI designs. These include regular architectures, built by interconnecting a large number of a few types of system elements on a single chip or wafer. The motivation for introducing fault-tolerance (redundancy) into these architectures is two-fold: yield enhancement and performance (like computational availability) improvement.Keywords
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