Configuration of VLSI Arrays in the Presence of Defects

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Abstract
The penalties for configuring VLSI arrays for yield enhancement are assessed. Each dement of the fabricated array is assumed to be defective with independent probability p. A fixed fractmn R of the elements are to be connected into a prespecified defect-free configuration by means of switched interconnections. The probability that this can be done, known as the yield, must be bounded away from zero. The additional interconnections required increase the integrated circuit's area by the area overhead ratio AOR. Propagation delay is determined by the maximum connection length d. The following results are shown. Connection of RN fixed pins to distinct nondefective elements from an N- element linear array requires d = O(log N), AOR = O(log N). Connection of RN pairs of elements from two N-element linear arrays requires only constant d and AOR. Connection of a chain ofRN 2 dements from an N x N array requires only constant d and AOR; this result is closely related to the percolation model of statistical physics. Connection of a V'-RN x d'-RN lattice from an N x N array requires d = (~( IV)-~ N). Algorithms are presented that connect any fraction R < I - p of the dements with yield approaching one as N increases.

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