Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance
- 27 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 767-770
- https://doi.org/10.1109/iedm.1998.746469
Abstract
This paper contributes the first study of manufacturing variation on interconnect timing performance in a high speed microprocessor. Also new in this paper is a methodology using timing analysis in conjunction with post-extraction net adjustment to account for interconnect structure variation (e.g., that arising due to pattern dependencies); this methodology is efficient enough to enable thousands of nets to be analyzed for variation and is compatible with current CAD tools.Keywords
This publication has 2 references indexed in Scilit:
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