A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery

1 February 2007

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01936530,p. 436-591
https://doi.org/10.1109/isscc.2007.373481

Abstract

A DSP-based low-power 12.5Gb/s SerDes using a baud-rate ADC and a digital data-path is developed for backplane data communication. A digital 2-tap FFE and a 5-tap DFE in the RX provide channel compensation. A BER of -15 is measured over legacy backplanes with 24dB loss at Nyquist. The power consumption and die area are 330mW and 0.45mm² per TX/RX pair

Keywords

This publication has 3 references indexed in Scilit:

A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization
IEEE Journal of Solid-State Circuits, 2005
Timing Recovery in Digital Synchronous Data Receivers
IEEE Transactions on Communications, 1976