A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications

30 August 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01936530,p. 68-585 Vol. 1
https://doi.org/10.1109/isscc.2005.1493872

Abstract

A 6.25 Gb/s serial receiver with a 4-tap adaptive DFE is implemented in a 0.13 /spl mu/m 7LM CMOS process. Direct cancellation of the first post-cursor ISI is achieved, enabling recovery of a data eye fully closed from channel losses and crosstalk. A BER<10/sup -15/ is measured over legacy backplane channels.

Keywords

BACKPLANES
DECISION FEEDBACK EQUALIZERS
CROSSTALK
INTERSYMBOL INTERFERENCE
BANDWIDTH
TRANSMITTERS
SIGNAL RESOLUTION
ACOUSTIC REFLECTION
NONLINEAR FILTERS
BIT ERROR RATE

This publication has 2 references indexed in Scilit:

Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2004
Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell
IEEE Journal of Solid-State Circuits, 2003