PASSOS: a different approach for assignment and scheduling for power, area and speed optimization in high-level synthesis
- 17 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 1, 339-342
- https://doi.org/10.1109/mwscas.1994.519252
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
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- PLS: a scheduler for pipeline synthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- SALSA: a new approach to scheduling with timing constraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- Low-power CMOS digital designIEEE Journal of Solid-State Circuits, 1992
- Algorithms for high-level synthesisIEEE Design & Test of Computers, 1989