Maximizing pin alignment in semi-custom chip circuit layout

This publication has 3 references indexed in Scilit:

• Maximizing pin alignment by pin permutations
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• Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
• Optimal Layout of CMOS Functional Arrays
  IEEE Transactions on Computers, 1981