A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
- 1 July 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 32 (7) , 1013-1026
- https://doi.org/10.1109/4.597292
Abstract
No abstract availableThis publication has 19 references indexed in Scilit:
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