Architectural and multiprocessor design verification of the PowerPC 604 data cache
- 19 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 383-388
- https://doi.org/10.1109/pccc.1995.472464
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- Designing the PowerPC 60X busIEEE Micro, 1994
- Verifying a multiprocessor cache controller using random test generationIEEE Design & Test of Computers, 1990