Verifying a multiprocessor cache controller using random test generation
- 1 August 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test of Computers
- Vol. 7 (4) , 13-25
- https://doi.org/10.1109/54.57906
Abstract
The design verification of the cache controller for SPUR, a shared-memory multiprocessor, is reported. The strategy was to develop a random tester that would generate and verify the complex interactions between multiple processors in functional simulation. Replacing the CPU model, the tester generates memory references by random selection from a script of actions and checks. It was easy to develop and detect over half the bugs uncovered during functional simulation. A prototype SPUR multiprocessor system that runs the Sprite operating system is being used for experiments in parallel programming. Results to data are described.Keywords
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