A 5 V-only 64K dynamic RAM based on high S/N design
- 1 October 1980
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 15 (5) , 846-854
- https://doi.org/10.1109/jssc.1980.1051481
Abstract
A 5 V-only 64K dynamic RAM is designed and fabricated using double poly-Si technology based on the 3 /spl mu/m design rule. The design features of this dynamic RAM are described. In particular, memory cell and S/N (signal/noise) designs are focused of a dynamic RAM with an on-chip bias generator. The device fabricated provides a typical access time of 120 ns and a 170 mW operating power, with minimized sense noise of less than 50 mV.Keywords
This publication has 8 references indexed in Scilit:
- Single 5-V, 64k RAM with Scaled-Down MOS StructureIEEE Journal of Solid-State Circuits, 1980
- Characteristics and limitation of scaled-down MOSFET's due to two-dimensional field effectIEEE Transactions on Electron Devices, 1979
- 1 /spl mu/m MOSFET VLSI technology. IV. Hot-electron design constraintsIEEE Journal of Solid-State Circuits, 1979
- A 64 Kbit MOS dynamic random access memoryIEEE Journal of Solid-State Circuits, 1979
- A fault-tolerant 64K dynamic RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- Design of ion-implanted MOSFET's with very small physical dimensionsIEEE Journal of Solid-State Circuits, 1974
- Optimization of the latching pulse for dynamic flip-flop sensorsIEEE Journal of Solid-State Circuits, 1974
- Fundamental limitations in microelectronics—I. MOS technologySolid-State Electronics, 1972