An improved frequency compensation technique for CMOS operational amplifiers
- 1 December 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 18 (6) , 629-633
- https://doi.org/10.1109/jssc.1983.1052012
Abstract
The commonly used two-stage CMOS operational amplifier suffers from two basic performance limitations due to the RC compensation network around the second gain stage. First, it provides stable operation for only a limited range of capacitive loads, and second, the power supply rejection shows severe degradation above the open-loop pole frequency. The technique described provides stable operation for a much larger range of capacitive loads, as well as much improved V/SUB BB/ power supply rejection over very wide bandwidths for the same basic operational amplifier circuit. The author presents a mathematical analysis of this new technique in terms of its frequency and noise characteristics followed by its implementation in all n-well CMOS process. Experimental results show 70-dB negative power supply rejection at 100 kHz and an input noise density of 58 nV/(Hz)/SUP 1/2/ at 1 kHz.Keywords
This publication has 6 references indexed in Scilit:
- Low-Power High-Drive CMOS Operational AmplifiersIEEE Journal of Solid-State Circuits, 1983
- A Single Chip Speech Synthesizer Using a Switched-Capacitor MultiplierIEEE Journal of Solid-State Circuits, 1983
- MOS operational amplifier design-a tutorial overviewIEEE Journal of Solid-State Circuits, 1982
- A single-chip CMOS PCM CODEC with filtersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- A high performance low power CMOS channel filterIEEE Journal of Solid-State Circuits, 1980
- High-performance NMOS operational amplifierIEEE Journal of Solid-State Circuits, 1978