A high performance low power CMOS channel filter
- 1 December 1980
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 15 (6) , 929-938
- https://doi.org/10.1109/jssc.1980.1051499
Abstract
A new CMOS PCM channel filter is described, which includes transmit and receive filters on a single die. This chip displays an idle-channel noise of typically 0 dBrnC0, a power supply rejection ratio of 40-50 dB at 1 kHz, and a fully operational power dissipation of only 35 mW, making it very cost effective in telecommunication switching systems. The design of this chip, including architectural, switched capacitor filter, and amplifier considerations is described, and typical experimental results are presented.Keywords
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