Signature Analysis: Simulation of Inventory, Cycle Time, and Throughput Trade-Offs in Wafer Fabrication
- 1 December 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Components, Hybrids, and Manufacturing Technology
- Vol. 9 (4) , 498-507
- https://doi.org/10.1109/tchmt.1986.1136668
Abstract
No abstract availableKeywords
This publication has 1 reference indexed in Scilit:
- Signature Analysis of Dispatch Schemes in Wafer FabricationIEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1986