Signature Analysis of Dispatch Schemes in Wafer Fabrication
- 1 December 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Components, Hybrids, and Manufacturing Technology
- Vol. 9 (4) , 518-525
- https://doi.org/10.1109/tchmt.1986.1136660
Abstract
No abstract availableThis publication has 4 references indexed in Scilit:
- Signature Analysis: Simulation of Inventory, Cycle Time, and Throughput Trade-Offs in Wafer FabricationIEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1986
- Modeling and Analysis of Three-Stage Transfer Lines with Unreliable Machines and Finite BuffersOperations Research, 1983
- A Review of Production SchedulingOperations Research, 1981
- A Survey of Scheduling RulesOperations Research, 1977