Silicon debug: scan chains alone are not enough
- 20 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
For today's multi-million transistor designs, existingdesign verification techniques cannot guarantee thatfirst silicon is designed error free. Therefore,techniques are necessary to efficiently debug first-silicon.In this article, we present a methodology fordebugging multiple clock domain systems-on-a-chip.In addition to scan chains, a set of Design-for-Debugmodules is designed into an IC to make itdebuggable. Debugger tool software interacts withthe on-chip DfD to make the debug features availablefrom a workstation.Keywords
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