Interface state creation and charge trapping in the medium-to-high gate voltage range (V/sub d//2or=V/sub d/) during hot-carrier stressing of n-MOS transistors
- 1 March 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 37 (3) , 744-754
- https://doi.org/10.1109/16.47781
Abstract
No abstract availableKeywords
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