A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
- 1 November 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 31 (11) , 1703-1714
- https://doi.org/10.1109/jssc.1996.542315
Abstract
This paper describes a 160 MHz 500 mW StrongARM microprocessor designed for low-power, low-cost applications. The chip imple-ments the ARM V4 instruction set, and is bus compatible with earlier implementations. The pin interface runs at 3.3 V but the internal power supplies can vary from 1.5 to 2.2 V, pro-viding various options to balance performance and power dissipation. At 160 MHz internal clock speed with a nominal Vdd of 1.65 V, it delivers 185 Dhrystone 2.1 MIPS while dissipating less than 450 mW. The range of operating points runs from 100 MHz at 1.65 V dissipating less than 300 mW to 200 MHz at 2.0 V for less than 900 mW. An on-chip PLL provides the internal clock based on a 3.68 MHz clock input. The chip contains 2.5 million transistors, 90% of which are in the two 16 kB caches. It is fabricatedKeywords
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