A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology
- 28 May 2008
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 43 (6) , 1414-1426
- https://doi.org/10.1109/jssc.2008.922719
Abstract
The design and experimental verification of a 75-GHz phase-locked loop (PLL) fabricated in 90-nm CMOS technology is presented. The circuit incorporates a three-quarter wavelength oscillator to achieve high-frequency operation and a novel phase-frequency detector (PFD) based on SSB mixers to suppress the reference feedthrough. The PLL demonstrates an operation range of 320 MHz and reference sidebands of less than -72 dBc while consuming 88 mW from a 1.45-V supply.Keywords
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