A board system for high-speed image analysis and neural networks
- 1 January 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Neural Networks
- Vol. 7 (1) , 214-221
- https://doi.org/10.1109/72.478407
Abstract
Two ANNA neural-network chips are integrated on a 6U VME board, to serve as a high-speed platform for a wide variety of algorithms used in neural-network applications as well as in image analysis. The system can implement neural networks of variable sizes and architectures, but can also be used for filtering and feature extraction tasks that are based on convolutions. The board contains a controller implemented with field programmable gate arrays (FPGA's), memory, and bus interfaces, all designed to support the high compute power of the ANNA chips. This new system is designed for maximum speed and is roughly 10 times faster than a previous board. The system has been tested for such tasks as text location, character recognition, and noise removal as well as for emulating cellular neural networks (CNN's). A sustained speed of up to two billion connections per second (GC/s) and a recognition speed of 1000 characters per second has been measured.Keywords
This publication has 11 references indexed in Scilit:
- Image recognition with an analog neural net chipPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Smart-pixel cellular neural networks in analog current-mode CMOS technologyIEEE Journal of Solid-State Circuits, 1994
- Neural networks at workIEEE Spectrum, 1993
- The CNN is universal as the Turing machineIEEE Transactions on Circuits and Systems I: Regular Papers, 1993
- Current-mode techniques for the implementation of continuous- and discrete-time cellular neural networksIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1993
- Application of the ANNA neural network chip to high-speed character recognitionIEEE Transactions on Neural Networks, 1992
- An 11-million Transistor Neural Network Execution EnginePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- An analog neural network processor with programmable topologyIEEE Journal of Solid-State Circuits, 1991
- CNN cloning template: hole-fillerIEEE Transactions on Circuits and Systems, 1990
- Cellular neural networks: theoryIEEE Transactions on Circuits and Systems, 1988