Local silicon-gate carbon nanotube field effect transistors using silicon-on-insulator technology
- 10 July 2006
- journal article
- Published by AIP Publishing in Applied Physics Letters
- Vol. 89 (2) , 023116
- https://doi.org/10.1063/1.2221515
Abstract
A local silicon-gate carbon nanotube field effect transistor (CNFET) configuration has been proposed and implemented for integration purpose. By combining the advantages of in situ carbon nanotube growth technology and the silicon-on-insulator technology, we have realized the CNFETs with individual device operation, low parasitic capacitance, high yield fabrication, and better compatibility to the complementary-metal-oxide-semiconductor (CMOS) process. The CNFETs show up-to-date electrical performance. The scaling effect of gate oxide is also explored. This configuration makes CNFET a step closer to the CMOS integrated circuit application.Keywords
This publication has 12 references indexed in Scilit:
- Benchmarking Nanotechnology for High-Performance and Low-Power Logic Transistor ApplicationsIEEE Transactions on Nanotechnology, 2005
- Silicon-on-Insulator Technology: Materials to VLSIPublished by Springer Nature ,2004
- Monolithic Integration of Carbon Nanotube Devices with Silicon MOS TechnologyNano Letters, 2003
- Carbon Nanotube Transistor Arrays for Multistage Complementary Logic and Ring OscillatorsNano Letters, 2002
- Vertical scaling of carbon nanotube field-effect transistors using top gate electrodesApplied Physics Letters, 2002
- Shell Filling and Exchange Coupling in Metallic Single-Walled Carbon NanotubesPhysical Review Letters, 2002
- Logic Circuits with Carbon Nanotube TransistorsScience, 2001
- Structural () Determination of Isolated Single-Wall Carbon Nanotubes by Resonant Raman ScatteringPhysical Review Letters, 2001
- Single- and multi-wall carbon nanotube field-effect transistorsApplied Physics Letters, 1998
- Synthesis of individual single-walled carbon nanotubes on patterned silicon wafersNature, 1998