A 25ns 256K CMOS SRAM
- 1 January 1986
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. XXIX, 250-251
- https://doi.org/10.1109/isscc.1986.1156929
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- A 4.5ns 256K CMOS SRAM with tri-level word linePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- A 256K CMOS SRAM with variable-impedance loadsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985