A 4.5ns 256K CMOS SRAM with tri-level word line
- 1 January 1985
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- A 20ns 64K CMOS SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A 64Kb full CMOS RAM with divided word line structurePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- A 64Kb CMOS RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982