A 20ns 64K CMOS SRAM

1 January 1984

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXVII, 222-223
https://doi.org/10.1109/isscc.1984.1156700

Abstract

A 19.0mm²64K×1 SRAM utilizing pulsed-word-line technique, P-well/bipolar technology, and 1.3μm gate MOS transistors, will be described. The RAM has typical address access time of 20ns and power dissipation of 70mW at 1 MHz cycle time.

Keywords

RANDOM ACCESS MEMORY
READ-WRITE MEMORY
CMOS TECHNOLOGY
MOSFETS
POWER DISSIPATION
FREQUENCY
MOS DEVICES
CLOCKS
ELECTRICAL RESISTANCE MEASUREMENT
SEMICONDUCTOR DEVICE MEASUREMENT

This publication has 2 references indexed in Scilit:

A 64Kb CMOS RAM
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1982
HI-CMOSII 4K static RAM
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1981