Approaching a machine-application bound in delivered performance on scientific code
- 1 January 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE
- Vol. 81 (8) , 1166-1178
- https://doi.org/10.1109/5.236193
Abstract
No abstract availableThis publication has 18 references indexed in Scilit:
- Hierarchical Performance Modeling With MACS: A Case Study Of The Convex C-240Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Polycyclic vector scheduling vs. chaining on 1-port vector supercomputersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Squeezing more CPU performance out of a Cray-2 by vector block schedulingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Register requirements of pipelined processorsPublished by Association for Computing Machinery (ACM) ,1992
- Instruction level profiling and evaluation of the IBM/6000ACM SIGARCH Computer Architecture News, 1991
- Vector register design for polycyclic vector schedulingPublished by Association for Computing Machinery (ACM) ,1991
- Machine organization of the IBM RISC System/6000 processorIBM Journal of Research and Development, 1990
- Decoupled access/execute computer architecturesACM Transactions on Computer Systems, 1984
- A Fortran compiler for the FPS-164 scientific computerPublished by Association for Computing Machinery (ACM) ,1984
- Efficient code generation for horizontal architecturesACM SIGARCH Computer Architecture News, 1982