Exploiting instruction-level parallelism for integrated control-flow monitoring
- 1 January 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 43 (2) , 129-140
- https://doi.org/10.1109/12.262118
Abstract
No abstract availableThis publication has 15 references indexed in Scilit:
- Saturation: reduced idleness for improved fault-tolerancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A superpipeline approach to the MIPS architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Architecture and implementation of a VLIW supercomputerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An instruction-level performance analysis of the Multiflow TRACE 14/300Published by Association for Computing Machinery (ACM) ,1991
- The nonuniform distribution of instruction-level and machine parallelism and its effect on performanceIEEE Transactions on Computers, 1989
- A VLIW architecture for a trace scheduling compilerACM SIGARCH Computer Architecture News, 1987
- Processor Control Flow Monitoring Using Signatured Instruction StreamsIEEE Transactions on Computers, 1987
- Concurrent Error Detection in Multiply and Divide ArraysIEEE Transactions on Computers, 1983
- Very Long Instruction Word architectures and the ELI-512Published by Association for Computing Machinery (ACM) ,1983
- Trace Scheduling: A Technique for Global Microcode CompactionIEEE Transactions on Computers, 1981