A 3D HDI ASP: a cost-effective alternative to WSI signal processors
- 7 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 267-276
- https://doi.org/10.1109/wafer.1989.47557
Abstract
A research project, in which various high-density interconnect (HDI) and wafer-scale integration (WSI) implementation variants of a common computer architecture, the associative string processor (ASP), are compared, is discussed. The ASP is a fault-tolerant and highly versatile massively parallel processor capable of sustaining high performance over a wide range of computationally intensive tasks and, unlike most other computer architectures, the ASP has been designed to exploit state-of-the-art microelectronic technology. The study indicates that, until the feasibility of WSI ASP technology has been proven, a 3-D HDI ASP seems to offer a cost-effective alternative technology for the development of highly compact massively parallel processors for aerospace and automotive applications Author(s) Warren, K.D. Brunel Univ., Uxbridge, UK Reche, J.H. ; Jacobi, W.J. ; Lea, R.M.Keywords
This publication has 1 reference indexed in Scilit:
- ASP: a cost-effective parallel microcomputerIEEE Micro, 1988