VLSI implementation of synchronization algorithms in a 100 Mbit/s digital receiver
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 589-593 vol.1
- https://doi.org/10.1109/glocom.1990.116578
Abstract
Digital VLSI implementation of the timing and carrier synchronization of digital receivers at very high data rates is addressed. The implementation of the synchronization algorithms for 100 Mb/s digital receiver for coded 8-PSK modulation is described. The digital receiver operates on a signal which is down-converted to baseband with a fixed-frequency oscillator and which is sampled at a fixed rate (no VCOs). The timing is recovered by estimating the timing offset and shifting the received samples by means of a digital interpolation. The carrier synchronization is carried out after matched filtering by estimating the carrier phase offset and rotating the samples accordingly.Keywords
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