A 100 Mbit/s Viterbi decoder chip: novel architecture and its realization
- 1 January 1990
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 463-467 vol.2
- https://doi.org/10.1109/icc.1990.117124
Abstract
Installing new high-speed digital microwave and satellite communication links often leads to the need for fast Viterbi decoders (VDs). However, the main unit of a VD contains a nonlinear data-dependent feedback loop that limits the maximum achievable throughput rate. A conventional realization of this loop leads to the problem that good decoder performance requires a large wordlength, whereas a high data rate requires a small wordlength. The authors present an architecture which eliminates this trade-off by bit-level parallel processing. The architecture was used in the design of a fabricated 115 Mb/s VD chip for an 8-PSK (phase-shift keying) trellis code. This represents the fastest single-chip VD built to date. The less complex design (Keywords
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