Cascaded feedforward architectures for parallel Viterbi decoding

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 978-981 vol.2
https://doi.org/10.1109/iscas.1990.112266

Abstract

The Viterbi algorithm (VA) is a common application of dynamic programming. Since it contains a nonlinear ACS (add-compare-select) feedback loop, this loop is the bottleneck in high-data-rate implementations. It is shown that, asymptotically, the ACS feedback no longer has to be processed recursively, i.e. there is no feedback, resulting in negligible performance loss. This can be exploited to derive purely feedforward architectures for Viterbi decoding, so that a modular cascadable implementation results. By designing one cascadable module, any speedup can be achieved simply by adding modules to the implementation. It is shown that optimization criteria, e.g. minimum latency or maximum hardware efficiency, are met by very different architectures.<>

Keywords

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