Universal-Vdd 0.65-2.0V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell

13 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01936530,p. 168-169,
https://doi.org/10.1109/isscc.2001.912589

Abstract

This 32 kB cache design operates from 120 MHz at 1.7 mW and 0.65V to 1.04 GHz at 530 mW and 2.0 V with a single internal supply using 0.18 /spl mu/m CMOS technology. The wide voltage operating range is achieved using a voltage-adapted timing-generation scheme with plural dummy cells and a lithographically-symmetric cell (LS-cell).

Keywords

TIMING
THRESHOLD VOLTAGE
FLUCTUATIONS
OPTICAL AMPLIFIERS
RANDOM ACCESS MEMORY
CMOS TECHNOLOGY
PULSE AMPLIFIERS
FREQUENCY
CIRCUIT TESTING
LOW VOLTAGE

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A replica technique for wordline and sense control in low-power SRAM's
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