Direct evaluation of gate line edge roughness impact on extension profiles in sub-50mn N-MOSFETs
- 19 April 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
We directly evaluated the impact of gate line edge roughness (LER) on two-dimensional carrier profiles in sub-50-nm n-FETs. Using scanning tunneling microscopy, we clearly observed that the roughness of the extension edges induced by the gate LER strongly depended on the implanted dose, pockets, and co-implantations. Impurity diffusion suppressed by a nitrogen (N) co-implant enhanced the roughness of the extension edges, which caused fluctuation in the device performance. We verified the expected impact of the N co-implant on the electrical performance of the n-FETs.Keywords
This publication has 2 references indexed in Scilit:
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