A study of two approaches for reconfiguring fault-tolerant systolic arrays
- 1 June 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 38 (6) , 833-844
- https://doi.org/10.1109/12.24292
Abstract
No abstract availableThis publication has 9 references indexed in Scilit:
- Restructuring for fault-tolerant systolic arraysIEEE Transactions on Computers, 1989
- Wafer-Scale Integration of Systolic ArraysIEEE Transactions on Computers, 1985
- Dynamically Restructurable Fault-Tolerant Processor Network ArchitecturesIEEE Transactions on Computers, 1985
- The Diogenes Approach to Testable Fault-Tolerant Arrays of ProcessorsIEEE Transactions on Computers, 1983
- Reconfigurable architectures for VLSI processing arraysPublished by Association for Computing Machinery (ACM) ,1983
- Area and Delay Penalties in Restructurable Wafer-Scale ArraysPublished by Springer Nature ,1983
- A Fault-Tolerant Communication Architecture for Distributed SystemsIEEE Transactions on Computers, 1982
- Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI DesignsIEEE Transactions on Computers, 1982
- Fault-tolerant wafer-scale architectures for VLSIACM SIGARCH Computer Architecture News, 1982