A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects
- 20 November 2006
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 41 (12) , 2921-2929
- https://doi.org/10.1109/jssc.2006.884389
Abstract
This paper presents a clock-and-data recovery (CDR) for pseudo-synchronous high-density link applications. The CDR is a first-order bang-bang (BB) topology implemented in a standard CMOS process and consists of a phase interpolator, a linear half-rate phase detector, an analog filter followed by a limiter and a digital loop filter operating at a reduced clock rate. A detailed BB CDR analysis derives the maximum tracking range, slew-rate limited jitter tolerance and maximum loop delay. The circuit is optimized for high speed as well as low area and power consumption. The CDR operates from 8-28 Gb/s at a BER of 0.35UIpp for jitter frequencies les100 MHz and the total timing jitter of the recovered half-rate output data amounts to 0.22 UIpp at a BER=10-12. The core CDR circuit occupies a chip area of 0.07 mm2 and consumes 98 mW from a 1.1-V supplyKeywords
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