A semidigital dual delay-locked loop
- 1 January 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 32 (11) , 1683-1692
- https://doi.org/10.1109/4.641688
Abstract
No abstract availableThis publication has 7 references indexed in Scilit:
- Analog Versus Digital Control of a Clock Synchronizer for 3 gb/s Data with 3.ov Differential EclPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A semi-digital DLL with unlimited phase shift capability and 0.08-400 MHz operating rangePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Low-jitter process-independent DLL and PLL based on self-biased techniquesIEEE Journal of Solid-State Circuits, 1996
- A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAMIEEE Journal of Solid-State Circuits, 1994
- Precise delay generation using coupled oscillatorsIEEE Journal of Solid-State Circuits, 1993
- PLL design for a 500 MB/s interfacePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- A variable delay line PLL for CPU-coprocessor synchronizationIEEE Journal of Solid-State Circuits, 1988