Parallel simulated annealing: accuracy vs. speed in placement

1 June 1989

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test of Computers

Vol. 6 (3) , 8-34
https://doi.org/10.1109/54.32410

Abstract

The techniques that researchers have used to control error in VLSI placement are surveyed. The author discusses the application of parallelism, synchronization with serial subsets, combining algorithms, periodic synchronization, shared-memory implementation, local-memory implementation, and connection Machine implementation. The issues of temporary versus cumulative error, task allocation, and error measurements are examined.

Keywords

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