A global delay model for domino cmos circuits with application to transistor sizing
- 1 May 1990
- journal article
- Published by Wiley in International Journal of Circuit Theory and Applications
- Vol. 18 (3) , 289-306
- https://doi.org/10.1002/cta.4490180306
Abstract
No abstract availableKeywords
This publication has 5 references indexed in Scilit:
- Zipper CMOSIEEE Circuits and Devices Magazine, 1986
- FFT scaling in Domino CMOS gatesIEEE Journal of Solid-State Circuits, 1985
- Analysis and design optimization of domino CMOS logic with application to standard cellsIEEE Journal of Solid-State Circuits, 1985
- NORA: a racefree dynamic CMOS technique for pipelined logic structuresIEEE Journal of Solid-State Circuits, 1983
- High-speed compact circuits with CMOSIEEE Journal of Solid-State Circuits, 1982