Analysis and design optimization of domino CMOS logic with application to standard cells
- 1 April 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 20 (2) , 523-530
- https://doi.org/10.1109/jssc.1985.1052338
Abstract
The application of domino logic to standard-cell-based design is discussed. Domino cells are compatible with static cells and can be used to achieve lower power consumption, as well as a reduction in area or an improvement in system speed. In order to optimise the delay/area performance of domino cells, an analytical model is presented and its validity verified by measurements on test cells implemented in both 5- and 3-/spl mu/m CMOS processes.Keywords
This publication has 5 references indexed in Scilit:
- Influence of series and parallel transistors on DC characteristics of CMOS logic circuitsMicroelectronics Journal, 1982
- High-speed compact circuits with CMOSIEEE Journal of Solid-State Circuits, 1982
- A design of CMOS polycell for LSI circuitsIEEE Transactions on Circuits and Systems, 1981
- A CMOS 32b single chip microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- The Simulation of MOS Integrated Circuits Using SPICE2Published by Defense Technical Information Center (DTIC) ,1980