Generation and analysis of very long address traces
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 270-279
- https://doi.org/10.1109/isca.1990.134535
Abstract
Existing methods of generating and analyzing traces suffer from a variety of limitations, including complexity, inaccuracy, short length, inflexibility, or applicability only to CISC (complex-instruction-set-computer) machines. The authors use a trace-generation mechanism based on link-time code modification which is simple to use, generates accurate long traces of multiuser programs, runs on a RISC (reduced-instruction-set-computer) machine, and can be flexibly controlled. Accurate performance data for large second-level caches can be obtained by on-the-fly analysis of the traces. A comparison is made of the performance of systems with 512 K to 16 M second-level caches, and it is show that, for today's large programs, second-level caches of more than 4 MB may be unnecessary. It is also shown that set associativity in second-level caches of more than 1 MB does not significantly improve system performance. In addition, the experiments provide insights into first-level and second-level cache line size.Keywords
This publication has 9 references indexed in Scilit:
- Techniques for efficient inline tracing on a shared-memory multiprocessorPublished by Association for Computing Machinery (ACM) ,1990
- A case for direct-mapped cachesComputer, 1988
- Serial and Parallel Solution of Large Scale Linear Programs by Augmented Lagrangian Successive OverrelaxationPublished by Springer Nature ,1988
- Timing Analysis and Performance Improvement of MOS VLSI DesignsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Global register allocation at link timePublished by Association for Computing Machinery (ACM) ,1986
- Instruction Cache Replacement Policies and OrganizationsIEEE Transactions on Computers, 1985
- The Magic VLSI Layout SystemIEEE Design & Test of Computers, 1985
- Sparsity-preserving sor algorithms for separable quadratic and linear programmingComputers & Operations Research, 1984
- Cache MemoriesACM Computing Surveys, 1982