An 833 MHz 1.5 W 18 Mb CMOS SRAM with 1.67 Gb/s/pin
- 7 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01936530,p. 266-267
- https://doi.org/10.1109/isscc.2000.839778
Abstract
The authors present an 18 Mb CMOS SRAM which operates at 833 MHz with 1.67 Gb/s/pin. The 114.4 mm/sup 2/ die consumes 1.5 W and is fabricated in a 0.18 /spl mu/m CMOS process with four levels of copper interconnect. The SRAM operates in two user-selectable double-data-rate modes (DDR and DDR2). High-frequency operation is achieved by solving three frequency-limiting issues identified in previous SRAM designs: managing data timing constraints associated with high-frequency operation in a high density SRAM core; maintaining coherency between SRAM output data timings and echo clock timings; and delivering symmetric data windows for 1 s and 0 s across a wide range of output driver supply levels.Keywords
This publication has 2 references indexed in Scilit:
- A 940 MHz data rate 8 Mb CMOS SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 μm CMOS processPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002