Test-set preserving logic transformations
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Logic transformations that preserve minimal or complete test sets of a combinational circuit are examined. Some basic transformation types are rigorously defined and characterized with respect to test-set preservation. The authors apply the transformations to adder design and show that any complete test set for a two-level adder is preserved on transformation to ripple-carry and carry-lookahead designs, thus verifying some recent simulation results.Keywords
This publication has 3 references indexed in Scilit:
- Testability preserving transformations in multi-level logic synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Detection of Multiple Faults in Combinational Logic NetworksIEEE Transactions on Computers, 1972