Testability preserving transformations in multi-level logic synthesis
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- On properties of algebraic transformation and the multifault testability of multilevel logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- An algorithmic branch and bound method for PLA test pattern generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Optimal logic synthesis and testability: two faces of the same coinPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A method to calculate necessary assignments in algorithmic test pattern generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A method of fault simulation based on stem regionsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Logic Minimization Algorithms for VLSI SynthesisPublished by Springer Nature ,1984