A folded-channel MOSFET for deep-sub-tenth micron era
Top Cited Papers
- 27 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 1032-1034
- https://doi.org/10.1109/iedm.1998.746531
Abstract
Deep-sub-tenth micron MOSFETs with gate length down to 20 nm are reported. To improve the short channel effect immunities, a novel folded channel transistor structure is proposed. The quasi-planar nature of this new variant of the vertical double-gate SOI MOSFETs simplified the fabrication process. The special features of the structure are: (1) a transistor is formed in a vertical ultra-thin Si fin and is controlled by a double-gate, which suppresses short channel effects; (2) the two gates are self-aligned and are aligned to the S/D; (3) S/D is raised to reduce the parasitic resistance; (4) new low-temperature gate or ultra-thin gate dielectric materials can be used because they are deposited after the S/D; and (5) the structure is quasi-planar because the Si fins are relatively short.Keywords
This publication has 2 references indexed in Scilit:
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- Impact of the vertical SOI 'DELTA' structure on planar device technologyIEEE Transactions on Electron Devices, 1991