Design of the Power6 Microprocessor

1 February 2007

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01936530,p. 96-97
https://doi.org/10.1109/isscc.2007.373605

Abstract

The POWER6trade microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability. The 341mm² 700M transistor dual-core microprocessor is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It operates at clock frequencies over 5GHz in high-performance applications, and consumes under 100W in power-sensitive applications.

Keywords

MICROPROCESSORS
VOLTAGE
FREQUENCY
LATCHES
CLOCKS
LOGIC ARRAYS
TIMING
CIRCUITS
HARDWARE
FEEDBACK

This publication has 1 reference indexed in Scilit:

4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2006