A 15 nanosecond complex multiplier-accumulator for FFTS
- 24 March 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 12, 527-530
- https://doi.org/10.1109/icassp.1987.1169603
Abstract
A recently announced bipolar fabrication process provides VLSI densities of high-speed ECL gates with substantially lower power dissipation. A multiplier-accumulator and multi-port register file have been produced with this process with worst-case cycle times of 15-nanoseconds. This paper describes the use of this complex multiplier-accumulator's new architectural features and speed with the register file to do high bandwidth fast Fourier transforms in a variety of different configurations. Author(s) Owen, R. Bipolar Integrated Technology, Inc., Saratoga, CaliforniaKeywords
This publication has 1 reference indexed in Scilit:
- Architectural considerations for a sub 10 nanosecond DSP building block familyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005