A 20-ns 128-kbit*4 high speed DRAM with 330-Mbit/s data rate
- 1 January 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 23 (5) , 1140-1149
- https://doi.org/10.1109/4.5936
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- The Future of DRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- A 30- mu A data-retention pseudostatic RAM with virtually static RAM modeIEEE Journal of Solid-State Circuits, 1988
- An experimental 35ns 1Mb biCMOS DRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- A 15-ns CMOS 64K RAMIEEE Journal of Solid-State Circuits, 1986
- Plate-noise analysis of an on-chip generated half-VDD biased-plate PMOS cell in CMOS DRAMsIEEE Journal of Solid-State Circuits, 1985
- Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMsIEEE Journal of Solid-State Circuits, 1984
- A 70 ns high density 64K CMOS dynamic RAMIEEE Journal of Solid-State Circuits, 1983