A 70 ns high density 64K CMOS dynamic RAM
- 1 October 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 18 (5) , 457-463
- https://doi.org/10.1109/JSSC.1983.1051978
Abstract
A 64K /spl times/ 1 CMOS dynamic RAM has been developed in a double-poly n-well CMOS technology with device scaling to the HMOS III level. A p-channel memory array with n-well protection reduced the operating soft error rate to less than one FIT. Periphery complexity is simplified due to CMOS circuits resulting in a size of 30,464 mil/SUP 2/ with a redundancy efficiency of 68%. The RAM has a typical access time of 70 ns and a CMOS standby power of 25 /spl mu/W. In addition, a static column design offers 35-ns data cycle time for high-bandwidth application.Keywords
This publication has 5 references indexed in Scilit:
- A 150ns 288k CMOS EPROM with redundancyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- A 64Kb full CMOS RAM with divided word line structurePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- A Hi-CMOSII 8Kx8 bit static RAMIEEE Journal of Solid-State Circuits, 1982
- An n-well CMOS dynamic RAMIEEE Transactions on Electron Devices, 1982
- HMOS-CMOS-a low-power high-performance technologyIEEE Journal of Solid-State Circuits, 1981