A Hi-CMOSII 8Kx8 bit static RAM
- 1 October 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 17 (5) , 793-798
- https://doi.org/10.1109/jssc.1982.1051820
Abstract
A Hi-CMOSII static RAM with 8K word by 8 bit organization has been developed. The RAM is fabricated using double polysilicon technology and p- and n-channel transistors having a typical gate polysilicon length of 2 /spl mu/m. The device was realized using low-power high-speed-oriented circuit design and a new redundancy circuit that utilizes laser diffusion programmable devices. The new RAM has an address access time of 65 ns, operating power dissipation of 200 mW, and standby dissipation of 10 /spl mu/W.Keywords
This publication has 9 references indexed in Scilit:
- A soft error rate model for MOS dynamic RAM'sIEEE Transactions on Electron Devices, 1982
- A high-speed Hi-CMOSII 4K static RAMIEEE Journal of Solid-State Circuits, 1981
- Advanced Hi-CMOS device technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- Redundancy techniques for fast static RAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- HI-CMOSII 4K static RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- 2K × 8 bit Hi-CMOS static RAM'sIEEE Transactions on Electron Devices, 1980
- A high-speed low-power Hi-CMOS 4K static RAMIEEE Transactions on Electron Devices, 1979
- A fault-tolerant 64K dynamic RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- A high-speed, low-power Hi-CMOS 4K static RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1978